1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technique, and more particularly, to an integrated circuit including a through chip via.
2. Description of the Related Art
Technology for packaging a semiconductor integrated circuit has been developed to satisfy the need for reliable, small-sized packaging. Particularly, various technologies regarding stack packaging have developed recently in response to the demand for the miniaturization and high performance of electrical/electronic devices.
A ‘stack package’ in the semiconductor technology field refers to a device that has two or more chips or packages stacked in a vertical direction. By implementing a stack package, it may be possible to form a semiconductor memory device with a capacity that has more than twice the capable memory capacity achieved through a typical semiconductor integration process. Because of the advantages of the stack package with respect to memory capacity, package density, and package size, research and development of the stack package has accelerated.
A stack package may be formed by stacking semiconductor chips, and then packaging the stacked semiconductor chips. Alternatively, the stack package may be formed by first packaging semiconductor chips, and then stacking the packaged semiconductor chips. The respective semiconductor chips in the stack package are electrically connected to each other through a metal wire or a through chip via such as a through silicon via (hereinafter referred to “TSV”). The stack package using a TSV has a structure such that semiconductor chips are physically and electrically connected to each other in a vertical direction by a TSV formed within a semiconductor substrate. The stack package, including a TSV, can reduce power consumption and signal delay, and increase an operation performance due to the increased bandwidth available for interfacing signals and power through the TSV.
FIG. 1 is a cross-sectional view illustrating a related integrated circuit including a TSV. For convenience, an integrated circuit including only one TSV is illustrated and described.
Referring to FIG. 1, an integrated circuit 10 includes a semiconductor substrate 12, TSV 14, and an isolation layer 16. The semiconductor substrate 12 is doped by a P-type impurity. TSV 14 is vertically formed and filled in the semiconductor substrate 12, such that the TSV 14 extends to a predetermined depth from the surface of the semiconductor substrate 12. The isolation layer 16 surrounds sidewalls of the TSV 14 to isolate the TSV 14 from the semiconductor substrate 12.
Herein, a manufacturing process of the integrated circuit 10 will be described. First, a hole is formed within the substrate 12. Next, the isolation layer 16 is formed along sidewalls of the hole. Then, a TSV 14 is formed by filling the remaining hole having the isolation layer 16 along the sidewalls. Finally, a grinding operation is performed onto the back side of the semiconductor substrate 12 until the back side of TSV 14 is exposed, so as to complete a semiconductor chip for the stack package. Accordingly, semiconductor chips manufactured as described above are stacked to form the stack package.
However, the conventional integrated circuit 10 may have disadvantages as discussed below.
First, before discussing the disadvantages of the conventional integrated circuit 10, TSV defects, which may occur during the insertion process of the TSV 14, are described.
FIGS. 2A and 2B illustrate examples of defects occurring in the TSV 14 shown in FIG. 1. Here, to say that the TSV 14 has defects means that the TSV 14 formed in the semiconductor substrate 12 is formed abnormally. The defects may occur depending on a process scheme, a process environment, the material used for the TSV 14, and so on.
For example, as shown in FIG. 2A, the TSV 14 may be formed without conforming to the surface of the semiconductor substrate 12. More specifically, a portion EM1 may occur over the TSV 14 because the TSV 14 does not fill the hole. That is, instead of being even with the surface of the semiconductor substrate 12, the TSV 14 may only be filled to a height below the surface of the semiconductor substrate 12. Due to this, circuits formed in an active region (not shown) of the semiconductor substrate 12 may not be connected to the TSV 14 through a conductive line. Accordingly, signals or power interfaced through the TSV 14 may not be provided to certain circuits.
Furthermore, as shown in FIG. 2B, the TSV 14 may be formed with one or more empty intermediate portions EM2. That is, the TSV 14 may not uniformly and smoothly fill the hole in the semiconductor substrate 12. Due to this, the resistance of the TSV 14 may increase. Accordingly, signals or power interfaced through the TSV 14 may not be provided properly to certain circuits.
As described above, TSV defects may occur during the formation process of the TSV 14 at a wafer level. However, only at a package level, occurring after the wafer level, is it possible to detect whether the TSV 14 has defects or not. At the package level, although defects of the TSV 14 are detected, no appropriate solutions currently exist to cure the defects. Furthermore, even if appropriate solutions did exist, additional costs and time would be needed to implement the solutions. Accordingly, it is desirable to detect whether TSV 14 has defects or not at the wafer level, instead of at the package level.